VLSI PROJECTS

S.NO

PROJECT TITLE

1.       

BCD adder designs based on three-input XOR and majority gates

2.       

High-speed area-efficient VLSI architecture of three-operand binary adder

3.       

64-bit ALU design using Vedic mathematics.

4.       

Single bit fault detecting ALU design using reversible gates

5.       

A design implementation and comparative analysis of advanced encryption standard (AES) algorithm.

6.       

Modified high speed 32-bit Vedic multiplier design and implementation.

7.       

An implementation of high-speed adaptive recursive Karatsuba multiplier with square root-carry-select-adder.

8.       

Design and implementation of low power and high-speed multiplier using Quaternary carry look-ahead adder

9.       

Approximate Multiplier Design Using Novel Dual-Stage 4 : 2 Compressors

10.   

An analysis of DCM-based true random number generator.

11.   

Low-power high-accuracy approximate multiplier using approximate higher order compressors.

12.   

An implementation of multiplier-accumulator unit using Vedic multiplier and reversible gates.

13.   

Elegant home with power saving, security, safety, remote controlling and auto control of water tank motor

14.   

Implementation of Electricity bill using VERILOG.

15.   

Realization of real time Candy mechanic using VERILOG

16.   

Design of Innovative automated teller machine (ATM) controller for financial transactions of having both deposit and withdraw using VERILOG HDL.

17.   

VLSI architecture for high performance wallace tree encoder

18.   

Implementation of First in First out (FIFO) design for avoiding data losses in transmission

19.   

Design of logically obfuscated n-bit ALU for enhanced security

20.   

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier

21.   

A low-power high-speed accuracy-controllable approximate multiplier design.

22.   

Performance analysis of parallel prefix adder for data path VLSI design.

23.   

Chip design for turbo encoder module for in-vehicle system.

24.   

A low-power yet high-speed configurable adder for approximate computing.

25.   

Low power 4×4-bit multiplier design using DADDA algorithm and optimized full adder

26.   

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA).

27.   

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

28.   

Design of efficient BCD adders in quantum-dot cellular automata

29.   

 Implementation of FSM based vending machine

30.   

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels.