VLSI INTERNSHIPS

 DIGITAL

  • Introduction to VLSI
  • Scope of VLSI
  • Today’s VLSI Design
  • VLSI Design Flow
  • Introduction to Digital Electronics
  • Universal Logic Elements
  • Combinational Circuits – Design and Analysis 
    • Arithmetic Circuits
    • Data processing Circuits
  • Sequential Circuits – Design and Analysis
    • Latches and Flip flops
    • Shift Registers and Counters
    • Memories – ROM and RAM
  • Finite State Machine
  • Sequence detection

 

 

Verilog HDL – RTL Coding

  • History of HDL
  • Design methodology
    • Top to bottom
    • Bottom to top
  • Hierarchical modeling concepts
    • Design methodologies
    • Modules
    • Instances
    • Design block
    • stimulus block
  • Lexical conventions
    • Whitespace
    • Comments
    • operators
  • Logical operators
    • Bitwise and Reduction operators
    • Concatenation and Conditional
    • Relational and arithmetic

 

 

 

    • Shift and Equality operators
    • Numberspecifications
    • Operators precedence
  • Data types
    • Value set
    • Nets
    • Registers
    • Vectors           
    • Integer
    • Real
    • Arrays
    • Parameters
    • Memories
    • Strings

 

  •  System tasks
    • $display
    • $monitor
    • $stop
    • $finish

 

    • $strobe
    • $random
  •  Compiler directives
    • `Define
    • `include
  •  Gate level modeling
  •  Data flow modeling
    • Continuous assignments
  • Behavioral modeling
    • Procedural blocks
    • Combinational always block
    • Sequential always block
  • Blocking and Non-Blocking assignments

 

  • Time scale precession
  • Loops
    • for loop
    • while loop
    • repeat
  •  Conditional statements

 

    • if/else
    • case, case(1), casex, casez
  •  Delays
  •  Tasks and functions
  •  Conditional compilation
  • Conditional execution
  • Finite State Machine
  • Basic FSM structure
  • Common FSM coding styles
  • Test Bench Development
    • Internal variable monitoring
    • Initial blocks
    • Include files
    • Comments